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FAN7930C -- Critical Conduction Mode PFC Controller
October 2010
FAN7930C Critical Conduction Mode PFC Controller
Features
PFC-Ready Signal Input Voltage Absent Detection Maximum Switching Frequency Limitation Internal Soft-Start and Startup without Overshoot Internal Total Harmonic Distortion (THD) Optimizer Precise Adjustable Output Over-Voltage Protection Open-Feedback Protection and Disable Function Zero-Current Detector (ZCD) 150s Internal Startup Timer MOSFET Over-Current Protection (OCP) Under-Voltage Lockout with 3.5V Hysteresis Low Startup and Operating Current Totem-Pole Output with High State Clamp +500/-800mA Peak Gate Drive Current 8-Pin SOP
Description
The FAN7930C is an active power factor correction (PFC) controller for boost PFC applications that operate in critical conduction mode (CRM). It uses a voltagemode PWM that compares an internal ramp signal with the error amplifier output to generate a MOSFET turn-off signal. Because the voltage-mode CRM PFC controller does not need rectified AC line voltage information, it saves the power loss of an input voltage sensing network necessary for a current-mode CRM PFC controller. FAN7930C provides over-voltage protection (OVP), open-feedback protection, over-current protection (OCP), input-voltage-absent detection, and undervoltage lockout protection (UVLO). The PFC-ready pin can be used to trigger other power stages when PFC output voltage reaches the proper level with hysteresis. The FAN7930C can be disabled if the INV pin voltage is lower than 0.45V and the operating current decreases to a very low level. Using a new variable on-time control method, THD is lower than the conventional CRM boost PFC ICs.
Related Resources
AN-8035 -- Design Consideration for Boundary Conduction Mode PFC Using FAN7930
Applications
Adapter Ballast LCD TV, CRT TV SMPS
Ordering Information
Part Number
FAN7930CM FAN7930CMX
Operating Temperature Range
-40 to +125C
Top Mark
FAN7930C
Package
8-Lead Small Outline Package (SOP)
Packing Method
Rail Tape & Reel
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Application Diagram
Figure 1.
Typical Boost PFC Application
Internal Block Diagram
Figure 2.
Functional Block Diagram
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Pin Configuration
Figure 3.
Pin Configuration (Top View)
Pin Definitions
Pin #
1 2 3 4 5 6 7 8
Name Description
INV RDY COMP CS ZCD GND OUT VCC This pin is the inverting input of the error amplifier. The output voltage of the boost PFC converter should be resistively divided to 2.5V. This pin is used to detect PFC output voltage reaching a pre-determined value. When output voltage reaches 89% of rated output voltage, this pin is pulled HIGH, which is an (open-drain) output type. This pin is the output of the transconductance error amplifier. Components for the output voltage compensation should be connected between this pin and GND. This pin is the input of the over-current protection comparator. The MOSFET current is sensed using a sensing resistor and the resulting voltage is applied to this pin. An internal RC filter is included to filter switching noise. This pin is the input of the zero-current detection block. If the voltage of this pin goes higher than 1.5V, then goes lower than 1.4V, the MOSFET is turned on. This pin is used for the ground potential of all the pins. For proper operation, the signal ground and the power ground should be separated. This pin is the gate drive output. The peak sourcing and sinking current levels are +500mA and -800mA, respectively. For proper operation, the stray inductance in the gate driving path must be minimized. This is the IC supply pin. IC current and MOSFET drive current are supplied using this pin.
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only.
Symbol
VCC IOH, IOL ICLAMP IDET VIN TJ TA TSTG ESD Supply Voltage Peak Drive Output Current
Parameter
Min.
-800 -10 -10
(1)
Max.
VZ +500 +10 +10 8.0 6.0 +150 +125 +150 2.5 2.0
Unit
V mA mA mA V C C C kV
Driver Output Clamping Diodes VO>VCC or VO<-0.3V Detector Clamping Diodes Error Amplifier Input, Output, ZCD and RDY Pin CS Input Voltage
(2)
-0.3 -10.0 -40 -65
Operating Junction Temperature Operating Temperature Range Storage Temperature Range Electrostatic Discharge Capability Human Body Model, JESD22-A114 Charged Device Model, JESD22-C101
Notes: 1. When this pin is supplied by external power sources by accident, its maximum allowable current is 50mA. 2. In case of DC input, acceptable input range is -0.3V~6V: within 100ns -10V~6V is acceptable, but electrical specifications are not guaranteed during such a short time.
Thermal Impedance
Symbol
JA
Parameter
Thermal Resistance, Junction-to-Ambient
(3)
Min.
150
Max.
Unit
C/W
Note: 3. Regarding the test environment and PCB type, please refer to JESD51-2 and JESD51-10.
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Electrical Characteristics
VCC = 14V, TA = -40C~+125C, unless otherwise specified.
Symbol
VCC Section VSTART VSTOP HYUVLO VZ VOP ISTART IOP IDOP IOPDIS VREF1 VREF1 VREF2 IEA,BS IEAS,SR IEAS,SK VEAH VEAZ gm tON,MAX1 tON,MAX2
Parameter
Start Threshold Voltage Stop Threshold Voltage UVLO Hysteresis Zener Voltage Recommended Operating Range Startup Supply Current Operating Supply Current Operating Current at Disable
Conditions
VCC Increasing VCC Decreasing ICC=20mA
Min.
11 7.5 3.0 20 13
Typ.
12 8.5 3.5 22
Max.
13 9.5 4.0 24 20
Units
V V V V V A mA mA A V mV mV A A A
Supply Current Section VCC=VSTART-0.2V Output Not Switching VINV=0V 90 2.465 120 1.5 2.5 160 2.500 0.1 20 VINV=1V~4V VINV=VREF -0.1V VINV=VREF +0.1V VINV=1V, VCS=0V 6.0 0.9 90 35.5 11.2 -0.5 -12 12 6.5 1.0 115 41.5 13.0 7.0 1.1 140 47.5 14.8 0.5 190 3.0 4.0 230 2.535 10.0
Dynamic Operating Supply Current 50kHZ, CI=1nF
Error Amplifier Section Voltage Feedback Input Threshold1 TA=25C Line Regulation Temperature Stability of VREF1 Input Bias Current Output Source Current Output Sink Current Output Upper Clamp Voltage Zero-Duty Cycle Output Voltage Transconductance
(4) (4)
VCC=14V~20V
V V mho s s
Maximum On-Time Section Maximum On-Time Programming 1 TA=25C, VZCD=1V T =25C, Maximum On-Time Programming 2 A IZCD=0.469mA Current-Sense Input Threshold Voltage Limit Input Bias Current Current-Sense Delay to Output
(4)
Current-Sense Section VCS ICS,BS tCS,D 0.7 VCS=0V~1V dV/dt=1V/100ns, from 0V to 5V -1.0 0.8 -0.1 350 0.9 1.0 500 V A ns
Continued on the following page...
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Electrical Characteristics
VCC = 14V, TA = -40C~+125C, unless otherwise specified.
Symbol
VZCD HYZCD VCLAMPH VCLAMPL IZCD,BS IZCD,SR IZCD,SK tZCD,D
Parameter
Input Voltage Threshold Detect Hysteresis
(4) (4)
Conditions
Min.
1.35 0.05
Typ.
1.50 0.10 6.2 0.65 -0.1
Max.
1.65 0.15 7.5 1.00 1.0 -4 10
Units
V V V V A mA mA ns
Zero-Current Detect Section
Input High Clamp Voltage Input Low Clamp Voltage Input Bias Current Source Current Capability Sink Current Capability
(4) (4)
IDET=3mA IDET= -3mA VZCD=1V~5V TA=25C TA=25C dV/dt=-1V/100ns, from 5V to 0V IO=-100mA, TA=25C IO=200mA, TA=25C CIN=1nF CIN=1nF VCC=20V, IO=100A VCC=5V, IO=100A
5.5 0 -1.0
Maximum Delay From ZCD to Output (4) Turn-On Output Voltage High Output Voltage Low Rising Time
(4) (4)
100
200
Output Section VOH VOL tRISE tFALL VO,MAX VO,UVLO tRST fMAX RDY Pin IRDY,SK IRDY,LK tSS VRDY HYRDY VOVP HYOVP VEN HYEN TSD THYS Output Sink Current IRDY,SK=2mA Output High Impedance 3 2.166 5 2.240 0.189 TA=25C TA=25C 2.620 0.120 0.40 0.050
(4)
9.2
11.0 1.0 50 50
12.8 2.5 100 100 14.5 1
V V ns ns V V s kHz mA mV A ms V V
Falling Time
Maximum Output Voltage Output Voltage with UVLO Activated Restart Timer Delay Maximum Switching Frequency
(4)
11.5
13.0
Restart / Maximum Switching Frequency Limit Section 50 250 1 150 300 2 320 300 350 4 500 1 7 2.314
VRDY,SAT Output Saturation Voltage Output Leakage Current Internal Soft-Soft
(4)
Soft-Start Timer Section UVLO Section Output Ready Voltage Output Ready Hysteresis OVP Threshold Voltage OVP Hysteresis Enable Threshold Voltage Enable Hysteresis Thermal Shutdown Temperature Hysteresis Temperature of TSD
(4)
Protections 2.675 0.175 0.45 0.10 140 60 2.730 0.230 0.50 0.15 155 V V V V C C
125
Note: 4. These parameters, although guaranteed by design, are not production tested.
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Comparison of FAN7530 and FAN7930C
Function FAN7530 FAN7930C FAN7930C Advantages
No External Circuit for PFC Output UVLO PFC Ready Pin None Integrated Reduce Power Loss and BOM Cost Caused by PFC Out UVLO Circuit Versatile Open-Drain Pin Abnormal CCM Operation Prohibited Frequency Limit None Integrated Abnormal Inductor Current Accumulation can be Prohibited Increase System Reliability by testing for input supply voltage Guarantee Stable Operation at Short Electric Power Failure Reduce Voltage and Current Stress at Startup None External None Integrated Internal 140C with 60C Hysteresis Eliminate Audible Noise due to Unwanted OVP Triggering No External Resistor is Needed Stable and Reliable TSD Operation Converter Temperature Range Limited Range
VIN-Absent Detection
None
Integrated
Soft-Start and Overshoot Prevention THD Optimizer TSD
Comparison between FAN7930 and FAN7930C
Function
RDY Threshold RDY Hysteresis Control Range Compensation
FAN7930
2.240V 0.600V None
FAN7930C
2.240V 0.189V Integrated
FAN7930C Remark
If PFC rated output voltage is assumed 390V: FAN7930: VRDY_HIGH trigger voltage = 349V VRDY_LOW trigger voltage = 256V FAN7930C: VRDY_HIGH trigger voltage = 349V VRDY_LOW trigger voltage = 320V
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Typical Performance Characteristics
Figure 4. Voltage Feedback Input Threshold 1 (VREF1) vs. TA
Figure 5. Start Threshold Voltage (VSTART) vs. TA
Figure 6. Stop Threshold Voltage (VSTOP) vs. TA
Figure 7. Startup Supply Current (ISTART) vs. TA
Figure 8. Operating Supply Current (IOP) vs. TA
Figure 9. Output Upper Clamp Voltage (VEAH) vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Typical Performance Characteristics
Figure 10. Zero Duty Cycle Output Voltage (VEAZ) vs. TA
Figure 11. Maximum On-Time Program 1 (tON,MAX1) vs. TA
Figure 12. Maximum On-Time Program 2 (tON,MAX2) vs. TA
Figure 13. Current-Sense Input Threshold Voltage Limit (VCS) vs. TA
Figure 14. Input High Clamp Voltage (VCLAMPH) vs. TA
Figure 15. Input Low Clamp Voltage (VCLAMPL) vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Typical Performance Characteristics
Figure 16. Output Voltage High (VOH) vs. TA
Figure 17. Output Voltage Low (VOL) vs. TA
Figure 18. Restart Timer Delay (tRST) vs. TA
Figure 19. Output Ready Voltage (VRDY) vs. TA
Figure 20. Output Saturation Voltage (VRDY,SAT) vs. TA
Figure 21. OVP Threshold Voltage (VOVP) vs. TA
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Applications Information
1. Startup: Normally, supply voltage (VCC) of a PFC block is fed from the additional power supply, which can be called standby power. Without this standby power, auxiliary winding for zero current detection can be used as a supply source. Once the supply voltage of the PFC block exceeds 12V, internal operation is enabled until the voltage drops to 8.5V. If VCC exceeds VZ, 20mA current is sinking from VCC.
Figure 23.
Circuit Around INV Pin
Figure 22.
Startup Circuit
2. INV Block: Scaled-down voltage from the output is the input for the INV pin. Many functions are embedded based on the INV pin: transconductance amplifier, output OVP comparator, disable comparator, and output UVLO comparator. For the output voltage control, a transconductance amplifier is used instead of the conventional voltage amplifier. The transconductance amplifier (voltagecontrolled current source) aids the implementation of the OVP and disable functions. The output current of the amplifier changes according to the voltage difference of the inverting and non-inverting input of the amplifier. To cancel down the line input voltage effect on power factor correction, the effective control response of the PFC block should be slower than the line frequency and this conflicts with the transient response of controller. Twopole one-zero type compensation may be used to meet both requirements. The OVP comparator shuts down the output drive block when the voltage of the INV pin is higher than 2.675V and there is 0.175V hysteresis. The disable comparator disables operation when the voltage of the inverting input is lower than 0.35V and there is 100mV hysteresis. An external small-signal MOSFET can be used to disable the IC, as shown in Figure 23. The IC operating current decreases to reduce power consumption if the IC is disabled. Error! Reference source not found. is the timing chart of the internal circuit near the INV pin when rated PFC output voltage is 390VDC and VCC supply voltage is 15V.
Figure 24.
Timing Chart for INV Block
3. RDY Output: When the INV voltage is higher than 2.24V, RDY output is triggered HIGH and lasts until the INV voltage is lower than 2.051V. When input AC voltage is quite high, for example 240VAC, PFC output voltage is always higher than RDY threshold, regardless of boost converter operation. In this case, the INV voltage is already higher than 2.24V before PFC VCC touches VSTART; however, RDY output is not triggered to HIGH until VCC touches VSTART. After boost converter operation stops, RDY is not pulled LOW because the INV voltage is higher than the RDY threshold. When VCC of the PFC drops below 5V, RDY is pulled LOW even though PFC output voltage is higher than threshold. The RDY pin output is open drain, so needs an external pullup resistor to supply the proper power source. The RDY pin output remains floating until VCC is higher than 2V.
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(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
(see Equation 1). Positive voltage is induced (see Equation 2) when the power switch turns off.
T VAUX = - AUX VAC TIND T VAUX = AUX (VPFCOUT - VAC ) TIND
FAN7930C -- Critical Conduction Mode PFC Controller
(1) (2)
where: VAUX is the auxiliary winding voltage; TIND is boost inductor turns; TIND auxiliary winding turns; VAC is input voltage for PFC converter; and VOUT_PFC is output voltage from the PFC converter.
Figure 25.
Two Cases of RDY Triggered HIGH Figure 27. Circuit Near ZCD
Because auxiliary winding voltage can swing from negative to positive voltage, the internal block in ZCD pin has both positive and negative voltage clamping circuits. When the auxiliary voltage is negative, internal circuit clamps the negative voltage at the ZCD pin around 0.65V by sourcing current to the serial resistor between the ZCD pin and the auxiliary winding. When the auxiliary voltage is higher than 6.5V, current is sinked through a resistor from the auxiliary winding to the ZCD pin.
Figure 28. Figure 26. Two Cases of RDY Triggered LOW
Auxiliary Voltage Depends on MOSFET Switching
4. Zero-Current Detection: Zero-current detection (ZCD) generates the turn-on signal of the MOSFET when the boost inductor current reaches zero using an auxiliary winding coupled with the inductor. When the power switch turns on, negative voltage is induced at the auxiliary winding due to the opposite winding direction
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
The auxiliary winding voltage is used to check the boost inductor current zero instance. When boost inductor current becomes zero, there is a resonance between boost inductor and all capacitors at the MOSFET drain pin: including COSS of the MOSFET; an external capacitor at the D-S pin to reduce the voltage rising and falling slope of the MOSFET; a parasitic capacitor at inductor; and so on to improve performance. Resonated voltage is reflected to the auxiliary winding and can be used for detecting zero current of boost inductor and
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valley position of MOSFET voltage stress. For valley detection, a minor delay by the resistor and capacitor is needed. A capacitor increases the noise immunity at the ZCD pin. If ZCD voltage is higher than 1.5V, an internal ZCD comparator output becomes HIGH and LOW when the ZCD goes below 1.4V. At the falling edge of comparator output, internal logic turns on the MOSFET.
current is reset to zero at the next switch on; inductor current builds up at every switching cycle and can be raised to very high current that exceeds the current rating of the power switch or diode. This can seriously damage the power switch and result in burn down. To avoid this, maximum switching frequency limitation is embedded. If ZCD signal is applied again within 3.3s after the previous rising edge of gate signal, this signal is ignored internally and FAN7930C waits for another ZCD signal. This slightly degrades the power factor performance at light load and high input voltage.
FAN7930C -- Critical Conduction Mode PFC Controller
Maximum Switching Frequency Limit Operation 5. Control: The scaled output is compared with the internal reference voltage and sinking or sourcing current is generated from the COMP pin by the transconductance amplifier. The error amplifier output is compared with the internal sawtooth waveform to give proper turn-on time based on the controller.
Figure 31.
Figure 29.
Auxiliary Voltage Threshold
When no ZCD signal is available, the PFC controller cannot turn on the MOSFET, so the controller checks every switching off time and forces MOSFET turn on when the off time is longer than 150s. This is called the restart timer, which triggers MOSFET turn-on at startup and may be used at the input voltage zero-cross period.
Figure 32.
Control Circuit
150s
Figure 30.
Restart Timer at Startup
Because the MOSFET turn-on depends on the ZCD input, switching frequency may increase to higher than several megahertz due to the miss-triggering or noise on the nearby ZCD pin. If the switching frequency is higher than needed for critical conduction mode (CRM), operation mode shifts to continuous conduction mode (CCM). In CCM, unlike CRM where the boost inductor
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0 13
Unlike a conventional voltage-mode PWM controller, FAN7930C turns on the MOSFET at the falling edge of ZCD signal. On-instance is determined by the external signal and the turn-on time lasts until the error amplifier output (VCOMP) and sawtooth waveform meet. When load is heavy, output voltage decreases, scaled output decreases, COMP voltage increases to compensate low output, turn-on time lengthens to give more inductor turn-on time, and increased inductor current raises the output voltage. This is how PFC negative feedback controller regulates output. The maximum of VCOMP is limited to 6.5V, which dictates the maximum turn-on time, and switching stops when VCOMP is lower than 1.0V.
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6. Soft-Start: When VCC reaches VSTART, the internal reference voltage is increased like a stair step for 5ms. As a result, VCOMP is also raised gradually and MOSFET turn-on time increases smoothly. This reduces voltage and current stress on the power switch during startup.
0.155 V / s
FAN7930C -- Critical Conduction Mode PFC Controller
Figure 33.
Turn-On Time Determination
The roles of PFC controller are regulating output voltage and input current shaping to increase power factor. Duty control based on the output voltage should be fast enough to compensate output voltage dip or overshoot. For the power factor, however, the control loop must not react to the fluctuating AC input voltage. These two requirements conflict; therefore, when designing a feedback loop, the feedback loop should be least 10 times slower than AC line frequency. That slow response is made by C1 at compensator. R1 makes gain boost around operation region and C2 attenuates gain at higher frequency. Boost gain by R1 helps raise the response time and improves phase margin.
Figure 36.
Soft-Start Sequence
Figure 34.
Compensators Gain Curve
For the transconductance error amplifier side, gain changes based on differential input. When the error is large, gain is large to make the output dip or peak to suppress quickly. When the error is small, low gain is used to improve power factor performance.
250mho
7. Startup without Overshoot: Feedback control speed of PFC is quite slow. Due to the slow response, there is a gap between output voltage and feedback control. That is why over-voltage protection (OVP) is critical at the PFC controller and voltage dip caused by fast load changes from light to heavy is diminished by a bulk capacitor. OVP is easily triggered at startup phase. Operation on and off by OVP at startup may cause audible noise and can increase voltage stress at startup, which is normally higher than in normal operation. This operation is better when soft-start time is very long. However, too much startup time enlarges the output voltage building time at light load. FAN7930C has overshoot avoidance at startup. During startup, the feedback loop is controlled by an internal proportional gain controller and, when the output voltage reaches the rated value, it switches to an external compensator after a transition time of 30ms. This internal proportional gain controller eliminates overshoot at startup and an external conventional compensator takes over successfully afterward.
115 mho
Figure 35.
Gain Characteristic
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(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
FAN7930C -- Critical Conduction Mode PFC Controller
Figure 37.
Startup Control without Overshoot Figure 39. Input and Output Current Near Input Voltage Peak Zero Cross
8. THD Optimization: Total Harmonic Distortion (THD) is the factor that dictates how closely input current shape matches sinusoidal form. The turn-on time of the PFC controller is almost constant over one AC line period due to the extremely low feedback control response. The turn-off time is determined by the current decrease slope of the boost inductor made by the input voltage and output voltage. Once inductor current becomes zero, resonance between COSS and the boost inductor makes oscillating waveforms at the drain pin and auxiliary winding. By checking the auxiliary winding voltage through the ZCD pin, the controller can check the zero current of boost inductor. At the same time, a minor delay is inserted to determine the valley position of drain voltage. The input and output voltage difference is at its maximum at the zero cross point of AC input voltage. The current decrease slope is steep near the zero cross region and more negative inductor current flows during a drain voltage valley detection time. Such a negative inductor current cancels down the positive current flows and input current becomes zero, called "zero-cross distortion" in PFC.
To improve this, lengthened turn-on time near the zero cross region is a well-known technique, though the method may vary and may be proprietary. FAN7930C optimizes this by sourcing current through the ZCD pin. Auxiliary winding voltage becomes negative when the MOSFET turns on and is proportional to input voltage. The negative clamping circuit of ZCD outputs the current to maintain the ZCD voltage at a fixed value. The sourcing current from the ZCD is directly proportional to the input voltage. Some portion of this current is applied to the internal sawtooth generator, together with a fixed-current source. Theoretically, the fixed-current source and the capacitor at sawtooth generator determine the maximum turn-on time when no current is sourcing at ZCD clamp circuit and available turn-on time gets shorter proportional to the ZCD sourcing current.
Figure 38. Input and Output Current Near Input Voltage Peak
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0 15
Figure 40.
Circuit of THD Optimizer
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FAN7930C -- Critical Conduction Mode PFC Controller
Figure 41.
Effect of THD Optimizer
By THD optimizer, turn-on time over one AC line period is proportionally changed, depending on input voltage. Near zero cross, lengthened turn-on time improves THD performance. 9. VIN Absent Detection: To save power loss caused by input voltage sensing resistors and to optimize THD, the FAN7930C omits AC input voltage detection. Therefore, no information about AC input is available from the internal controller. In many cases, the VCC of PFC controller is supplied by a independent power source, like standby power. In this scheme, some mismatch may exist. For example, when the electric power is
suddenly interrupted during two or three AC line periods; VCC is still live during that time, but output voltage drops because there is no input power source. Consequently, the control loop tries to compensate for the output voltage drop and VCOMP reaches its maximum. This lasts until AC input voltage is live again. When AC input voltage is live again, high VCOMP allows high switching current and more stress is put on the MOSFET and diode. To protect against this, FAN7930C checks if the input AC voltage exists. If input does not exist, soft-start is reset and waits until AC input is live again. Soft-start manages the turn-on time for smooth operation when it detects AC input is applied again and applies less voltage and current stress on startup. 10. Current Sense: The MOSFET current is sensed using an external sensing resistor for over-current protection. If the CS pin voltage is higher than 0.8V, the over-current protection comparator generates a protection signal. An internal RC filter of 40k and 8pF is included to filter switching noise. 11. Gate Driver Output: FAN7930C contains a single totem-pole output stage designed for a direct drive of the power MOSFET. The drive output is capable of up to +500/-800mA peak current with a typical rise and fall time of 50ns with 1nF load. The output voltage is clamped to 13V to protect the MOSFET gate even if the VCC voltage is higher than 13V.
VOUT VIN
Though VIN is eliminated, operation of controller is normal due to the large bypass capacitor.
VAUX
MOSFET gate
DMAX fMIN
fMIN
DMIN
NewVCOMP VIN Absence Detected
IDS
Smooth Soft-Start t
FAN7930 Rev.00
Figure 42.
Operation without VIN Absent Circuit
Figure 43.
Operation with VIN Absent Circuit
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
PCB Layout Guide
PFC block normally handles high switching current and the voltage low energy signal path can be affected by the high energy path. Cautious PCB layout is mandatory for stable operation. 1. The gate drive path should be as short as possible. The closed-loop that runs from the gate driver, MOSFET gate, and MOSFET source to ground of PFC controller should be as close as possible. This is also crossing point between power ground and signal ground. Power ground path from the bridge diode to the output bulk capacitor should be short and wide. The sharing position between power ground and signal ground should be only at one position to avoid ground loop noise. Signal path of PFC controller should be short and wide for external components to contact. PFC output voltage sensing resistor is normally high to reduce current consumption. This path can be affected by external noise. To reduce noise potential at the INV pin, a shorter path for output sensing is recommended. If a shorter path is not possible, place some dividing resistors between PFC output and the INV pin -- closer to the INV pin is better. Relative high voltage close to the INV pin can be helpful. ZCD path is recommended close to auxiliary winding from boost inductor and to the ZCD pin. If that is difficult, place a small capacitor (below 50pF) to reduce noise. The switching current sense path should not share with another path to avoid interference. Some additional components may be needed to reduce the noise level applied to the CS pin. 5. A stabilizing capacitor for VCC is recommended as close as possible to the VCC and ground pins. If it is difficult, place the SMD capacitor as close to the corresponding pins as possible.
2.
3.
Figure 44.
Recommended PCB Layout
4.
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
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FAN7930C -- Critical Conduction Mode PFC Controller
Typical Application Circuit
Application
LCD TV Power Supply
Device
FAN7930C
Input Voltage Range
90-265VAC
Rated Output Power
195W
Output Voltage (Maximum Current)
390V (0.5A)
Features
Average efficiency of 25%, 50%, 75%, and 100% load conditions is higher than 95% at universal input. Power factor at rated load is higher than 0.98 at universal input. Total Harmonic Distortion (THD) at rated load is lower than 15% at universal input.
Key Design Notes
When auxiliary VCC supply is not available, VCC power can be supplied through Zero Current Detect (ZCD) winding. The power consumption of R103 is quite high, so its power rating needs checking. Because the input bias current of INV pin is almost zero, output voltage sensing resistors (R112~R115) should be as high as possible. However, too-high resistance makes the node susceptible to noise. Resistor values need to strike a balance between power consumption and noise immunity. Quick-charge diode D106 can be eliminated. Without D106, system operation is normal due to the controller's highly reliable protection features.
1. Schematic
Optional D106 600V 3A 230mH, 49:6 BD101, 600V,15A LP101,EER3124N R112 3.9M R103, 10k,1W C104, 12nF D102, UF4004 FAN7930C 8 7 VCC Out 5 ZC D CS 4 3 Com 2p INV 1 RD Y GND 6 C109 ,47n F D101,1N474 6 VAUX R102, 330k C1030,68m F,630Vdc TH101 ,5D15 D105 600V 8A
DC OUTPUT
R113 3.9M
R109 47 Q101 FCPF 20N60 R108 D103,1N414 8 4.7
R104, 30k
R114 3.9M
C111 220mF, 450V
C102, 680nF
C105, 100nF
C107 ,33m F
LF101 ,23mH C115 ,2.2n F C101, 220nF R101,1MJ ZNR101 ,10D471 FS101, 250V,5 A
R111 0.08, 5W
D104,1N414 8
R115 75k
R110,10k
R107 C108, ,10k 220nF
C114 ,2.2n F
C112,470p F
C110,1n F
VCC for another power stage
Circuit for VCC. If external VCC is used, this circuit is not needed. Circuit for VCC for another power stage thus components structure and values may vary.
Figure 45.
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
Demonstration Circuit
www.fairchildsemi.com 18
FAN7930C -- Critical Conduction Mode PFC Controller
2. Transformer
Figure 46.
Transformer Schematic Diagram
3. Winding Specification
Position No
Np
Pin (S F)
9, 10 7, 8
Wire
0.1x50
Turns
49
Winding Method
Solenoid Winding
Barrier Tape TOP BOT Ts
1
Bottom
Insulation: Polyester Tape t = 0.025mm, 3 Layers NAUX 24 0.3 6 Solenoid Winding
Top
Insulation: Polyester Tape t = 0.025mm, 4 Layers
4. Electrical Characteristics
Pin
Inductance 9, 10 7, 8
Specification
230H 7%
Remark
100kHz, 1V
5. Core & Bobbin
Core: EER3124, Samhwa (PL-7) (Ae=97.9mm ) Bobbin: EER3124
2
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
www.fairchildsemi.com 19
FAN7930C -- Critical Conduction Mode PFC Controller
6. Bill of Materials
Part #
R101 R102 R103 R104 R107 R108 R109 R110 R111 R112, 113, 114 R115 C101 C102 C103 C104 C105 C107 C108 C109 C110 C112 C111 C114 C115
Value
Resister 1M 330k 10k 30k 10k 4.7k 47k 10k 0.80k 3.9k 75k Capacitor 220nF/275VAC 680nF/275VAC 0.68F/630V 12nF/50V 100nF/50V 33F/50V 220nF/50V 47nF/50V 1nF/50V 47nF/50V 220F/450V 2.2nF/450V 2.2nF/450V
Note
1W 1/2W 1W 1/4W 1/4W 1/4W 1/4W 1/4W 5W 1/4W 1/4W
Part #
Q101 D101 D102 D103 D104 D105 D106
Value
Switch FCPF20N60 1N4746 UF4004 1N4148 1N4148
Note
20A, 600V, SuperFET 1W, 18V, Zener Diode 1A, 400V Glass Passivated High-Efficiency Rectifier 1A, 100V Small-Signal Diode 1A, 100V Small-Signal Diode 8A, 600V, General-Purpose Rectifier 3A, 600V, General-Purpose Rectifier
Diode
IC101
FAN7930C Fuse
CRM PFC Controller
Box Capacitor Box Capacitor Box Capacitor Ceramic Capacitor SMD (1206) Electrolytic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Ceramic Capacitor Electrolytic Capacitor Box Capacitor Box Capacitor
FS101 TH101 BD101
5A/250V NTC 5D-15 Bridge Diode 15A, 600V Line Filter 23mH Transformer EER3124 ZNR 10D471 Ae=97.9mm
2
LF101 T1 ZNR101
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
www.fairchildsemi.com 20
FAN7930C -- Critical Conduction Mode PFC Controller
Physical Dimensions
5.00 4.80 3.81
8 5
B
A
0.65
6.20 5.80
1.75 4.00 3.80 5.60
PIN ONE INDICATOR
1
4
1.27 0.25 0.25 0.10 CBA
(0.33)
1.27
LAND PATTERN RECOMMENDATION SEE DETAIL A
1.75 MAX 0.51 0.33 R0.10 R0.10
C
0.25 0.19 0.10 C
OPTION A - BEVEL EDGE
0.50 x 45 0.25
GAGE PLANE
0.36
OPTION B - NO BEVEL EDGE
NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE CONFORMS TO JEDEC MS-012, VARIATION AA, ISSUE C, B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS DO NOT INCLUDE MOLD FLASH OR BURRS. D) LANDPATTERN STANDARD: SOIC127P600X175-8M. E) DRAWING FILENAME: M08AREV13
8 0
0.90 0.40
SEATING PLANE
(1.04)
DETAIL A
SCALE: 2:1
Figure 47.
8-Lead Small Outline Package (SOP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild's worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor's online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/.
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
www.fairchildsemi.com 21
FAN7930C -- Critical Conduction Mode PFC Controller
(c) 2010 Fairchild Semiconductor Corporation FAN7930C * Rev. 1.0.0
www.fairchildsemi.com 22

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